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INTEGRATED CIRCUITS
DATA SHEET
UDA1328T Multi-channel filter DAC
Preliminary specification Supersedes data of 1999 Oct 12 File under Integrated Circuits, IC01 2000 Jan 04
Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.7.1 8.7.2 8.7.3 8.8 8.8.1 8.8.2 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 FEATURES General Multiple format input interface Multi-channel DAC Advanced audio configuration APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION System clock Application modes Interpolation filter (DAC) Digital silence detection Noise shaper Filter Stream DAC Static Mode System clock setting De-emphasis control Digital interface formats L3 mode Digital interface formats L3 address L3 INTERFACE DESCRIPTION Address mode Data transfer mode Programming the sound processing and other features Reset bit System clock frequency Data input format Quick mute Power control Feature settings Volume control Sub volume control Mute Digital silence mode De-emphasis Output polarity control 19.2 19.3 19.4 19.5 20 21 10 11 12 13 14 15 16 17 18 19 19.1 LIMITING VALUES HANDLING
UDA1328T
THERMAL CHARACTERISTICS QUALITY SPECIFICATION DC CHARACTERISTICS AC CHARACTERISTICS (ANALOG) AC CHARACTERISTICS (DIGITAL) APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
1 1.1 FEATURES General
UDA1328T
* 2.7 to 3.6 V power supply * 5 V tolerant TTL compatible inputs * Selectable control via L3 microcontroller interface or via static pin control * Multi-channel integrated digital filter plus non-inverting Digital-to-Analog Converter (DAC) * Supports sample frequencies between 5 and 100 kHz * Digital silence detection (output) * Slave mode only applications * No analog post filtering required for DAC * Easy application. 1.2 Multiple format input interface 3 GENERAL DESCRIPTION
2
APPLICATIONS
This multi-channel DAC is eminently suitable for DVD like applications in which 5.1 channel encoded signals are used.
* I2S-bus, MSB-justified and LSB-justified format compatible (in L3 mode) * I2S-bus and LSB-justified format compatible * 1fs input format data rate. 1.3 Multi-channel DAC
The UDA1328 is a single-chip 6-channel DAC employing bitstream conversion techniques, which can be used either in L3 microcontroller mode or in static pin mode. The UDA1328 supports the I2S-bus data format with word lengths of up to 24 bits, the MSB-justified data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 18, 20 and 24 bits. All digital sound processing features can be controlled with the L3 interface e.g. volume control, selecting digital silence type, output polarity control and mute. Also system features such as power control, digital silence detection mode and output polarity control. Under static pin control, via static pins, the system clock can be set to either 256fs or 384fs support, digital de-emphasis can be set, there is digital mute and the digital input formats can also be set.
* 6-channel DAC with power on/off control * Digital logarithmic volume control via L3; volume can be set for each of the channels individually * Digital de-emphasis for 32, 44.1, 48 and 96 kHz fs via L3 and, for 32, 44.1 and 48 kHz in static mode * Soft or quick mute via L3 * Output signal polarity control via L3 microcontroller interface. 1.4 Advanced audio configuration
* 6-channel line output (under L3 volume control) * A stereo differential output (channel 1 and channel 2) for improved performance * High linearity, wide dynamic range, low distortion. 4 ORDERING INFORMATION TYPE NUMBER UDA1328T PACKAGE NAME SO32 DESCRIPTION plastic small outline package; 32 leads; body width 7.5 mm VERSION SOT287-1
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
5 QUICK REFERENCE DATA SYMBOL Supplies VDDA VDDD IDDA IDDD Tamb Vo(rms) (THD + N)/S analog supply voltage digital supply voltage analog supply current digital supply current ambient temperature 6 channels active 2.7 2.7 - - -40 notes 1 and 2 at 0 dB fs = 48 kHz fs = 96 kHz at -60 dB; A-weighted fs = 48 kHz fs = 96 kHz S/N signal-to-noise ratio code = 0; A-weighted fs = 48 kHz fs = 96 kHz DAC: channels 3 to 6 (channels 1 and 2 non-differential) Vo(rms) (THD + N)/S output voltage (RMS value) total harmonic distortion plus noise-to-signal ratio note 1 at 0 dB fs = 48 kHz fs = 96 kHz at -60 dB; A-weighted fs = 48 kHz fs = 96 kHz S/N signal-to-noise ratio code = 0; A-weighted fs = 48 kHz fs = 96 kHz cs Notes 1. The output voltage scales proportionally with the power supply voltage. 2. In this case the two outputs per channel (for channels 1 and 2) are combined. channel separation - - - 103 101 100 - - - - - -43 -41 - - - - -90 -85 - 1 - - - 106 104 - - - - -46 -44 - - - - -95 -90 - 3.3 3.3 28 11 - 2 PARAMETER CONDITIONS MIN. TYP.
UDA1328T
MAX.
UNIT
3.6 3.6 - - +85 - -88 -
V V mA mA C V dB dB dB dB dB dB V dB dB dB dB dB dB dB
DAC: channels 1 and 2 differential output voltage (RMS value) total harmonic distortion plus noise-to-signal ratio
-83 -
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
6 BLOCK DIAGRAM
UDA1328T
handbook, full pagewidth
VDDD 21
VSSD 20
UDA1328T
BCK WS DATAI12 DATAI34 DATAI56 10 11 12 13 14 DIGITAL INTERFACE CONTROL INTERFACE
9 23 24 25 18 19 17
STATIC MUTE DEEM1 DEEM0 L3CLOCK L3DATA L3MODE
VOLUME/MUTE/DE-EMPHASIS
26
DS
INTERPOLATION FILTER TEST1 SYSCLK 27 16 6-CHANNEL NOISE SHAPER 8 22 TEST3 TEST2
VOUT1P VOUT1N
28 29
DAC
DAC
32 31
VOUT2P VOUT2N
DAC VOUT3 1
DAC 2 VOUT4
DAC VOUT5 4
DAC 5 VOUT6
6 VDDA
7, 15 n.c.
3 VSSA
30
MGR979
Vref
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
7 PINNING SYMBOL VOUT3 VOUT4 VSSA VOUT5 VOUT6 VDDA n.c. TEST3 STATIC BCK WS DATAI12 DATAI34 DATAI56 n.c. SYSCLK L3MODE L3CLOCK L3DATA VSSD VDDD TEST2 MUTE DEEM1 DEEM0 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DESCRIPTION channel 3 analog output channel 4 analog output analog ground channel 5 analog output channel 6 analog output analog supply voltage not connected (reserved)
handbook, halfpage
UDA1328T
test output 3 static mode/L3 mode switch input bit clock input word select input data input channel 1 and 2 data input channel 3 and 4 data input channel 5 and 6 not connected (reserved) system clock: 256fs, 384fs, 512fs and 768fs L3 mode selection input L3 clock input L3 data input digital ground digital supply voltage test output 2 static mute control input DEEM control 1 input (static mode) L3 address select (L3 mode)/DEEM control 0 input (static mode) digital silence detect output test input 1 channel 1 analog output P channel 1 analog output N DAC reference voltage channel 2 analog output N channel 2 analog output P
VOUT3 1 VOUT4 2 VSSA 3 VOUT5 4 VOUT6 5 VDDA 6 n.c. 7 TEST3 8
32 VOUT2P 31 VOUT2N 30 Vref 29 VOUT1N 28 VOUT1P 27 TEST1 26 DS 25 DEEM0
UDA1328T
STATIC 9 BCK 10 WS 11 DATAI12 12 DATAI34 13 DATAI56 14 n.c. 15 SYSCLK 16
MGR980
24 DEEM1 23 MUTE 22 TEST2 21 VDDD 20 VSSD 19 L3DATA 18 L3CLOCK 17 L3MODE
DS TEST1 VOUT1P VOUT1N Vref VOUT2N VOUT2P
26 27 28 29 30 31 32
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
8 8.1 FUNCTIONAL DESCRIPTION System clock 8.4 Digital silence detection
UDA1328T
The UDA1328 operates in slave mode only, this means that in all applications the system must provide the system clock. The system frequency is selectable. The options are 256fs, 384fs, 512fs and 768fs for the L3 mode and 256fs or 384fs for the static mode. The system clock must be frequency-locked to the digital interface signals. It should be noted that the UDA1328 can operate from 5 to 100 kHz sampling frequency (fs). However in 768fs mode the sampling frequency must be limited to 55 kHz. 8.2 Application modes
The UDA1328 can detect digital silence conditions in channels 1 to 6, and report this via the output pin DS. This function is implemented to allow for external manipulation of the audio signal in the absence of program material, such as muting or recorder control. An active LOW output is produced at the DS pin if the channels selected via L3 or for all channels in static mode, carries all zeroes for at least 9600 consecutive audio samples (equals 200 ms for fs = 48 kHz). The DS pin is also active LOW when the output is digitally muted either via the L3 interface or via the STATIC pin. In static mode all channels participate in the digital silence detection. In L3 mode control each channel can be set, either to participate in the digital silence detection or not. 8.5 Noise shaper
Operating mode can be set with the STATIC pin, either to L3 mode (STATIC = LOW) or to the static mode (STATIC = HIGH). See Table 1 for pin functions in the static mode. Table 1 Mode selection in the static mode PIN L3CLOCK L3MODE L3DATA MUTE DEEM1 DEEM0 Notes 1. SF1 and SF0 are the Serial Format inputs (2-bit). 2. X means that the pin has no function in this mode and can best be connected to ground. 8.3 Interpolation filter (DAC) L3 MODE L3CLOCK L3MODE L3DATA X(2) X(2) L3ADR STATIC MODE clock select SF1(1) SF0(1) MUTE DEEM1 DEEM0
The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC). 8.6 Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post-filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage. 8.7 Static mode
The digital filter interpolates from 1 to 128fs by cascading a half-band filter and a FIR filter, see Table 2. The overall filter characteristic of the digital filters is illustrated in Fig.3, and the pass-band ripple is illustrated in Fig.4. Both figures are with a 44.1 kHz sampling frequency. Table 2 Interpolation filter characteristics CONDITION 0 to 0.45fs >0.55fs 0 to 0.45fs - VALUE (dB) 0.02 -55 >114 -3.5
The UDA1328 is set to static mode by setting the STATIC pin HIGH. The function of 6 pins of the device now get another function as can be seen in Table 1. 8.7.1 SYSTEM CLOCK SETTING
ITEM Pass-band ripple Stop band Dynamic range DC gain
In static mode pin 18 (L3CLOCK) is used to select the system clock setting. When pin 18 is LOW, the device is in 256fs mode, when pin 18 is HIGH the device is in 384fs mode.
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
8.7.2 DE-EMPHASIS CONTROL 8.8 L3 mode
UDA1328T
In static pin mode the pins DEEM0 and DEEM1 control the de-emphasis mode; see Table 3. Table 3 De-emphasis control DEEM1 0 0 1 1 DEEM0 0 1 0 1
The device is set to L3 mode by setting the STATIC pin to LOW. The device can then be controlled via the L3 microcontroller interface (see Chapter 9). 8.8.1 DIGITAL INTERFACE FORMATS
DEEM MODE No de-emphasis 32 kHz de-emphasis 44.1 kHz de-emphasis 48 kHz de-emphasis 8.7.3
The following interface formats can be selected in the L3 mode: * I2S-bus with data word length of up to 24 bits * MSB-justified with data word length of up to 24 bits * LSB-justified format with data word length of 16, 18, 20 or 24 bits. 8.8.2 L3 ADDRESS
DIGITAL INTERFACE FORMATS
In static pin mode the digital audio interface formats can be selected via pin 17 (SF1) and 19 (SF0). The following interface formats can be selected (see also Table 4): * I2S-bus with data word length of up to 24 bits * LSB-justified format with data word length of 16, 20 or 24 bits. Table 4 Input format selection in the static mode SF1 0 0 1 1 SF0 0 1 0 1
The UDA1328 can be addressed via the L3 microcontroller interface using one of two addresses. This is done in order to individually control the UDA1328 and other Philips DACs or CODECs via the same L3 bus. The address can be selected using pin 25 (DEEM0) in L3 mode. When pin 25 is set LOW, the address is 000100. When pin 25 is set HIGH the address is 000101.
INPUT FORMAT I2S-bus LSB-justified 16 bits LSB-justified 20 bits LSB-justified 24 bits
It should be noted that the digital audio interface holds that the BCK frequency can be 64 times the WS maximum frequency, or fBCK 64 x fWS
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
UDA1328T
MGR981
handbook, halfpage
0
volume (dB) -20
-40
-60
-80
-100
0
40
80
120
160 200 f (kHz)
fs = 6.14400 MHz
Fig.3 Overall frequency characteristics.
handbook, halfpage
-3.45
MGR982
Vo (dB) -3.47
-3.49
-3.51
-3.53
0
10
20
f (kHz)
30
fs = 6.14400 MHz
Fig.4 Pass-band ripple of all filters.
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andbook, full pagewidth
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Philips Semiconductors
Multi-channel filter DAC
WS 1 BCK 2 3
LEFT >=8 1 2 3
RIGHT
>=8
DATA
MSB
B2
MSB
B2
MSB
INPUT FORMAT I2S
WS
LEFT 16 15 2 1
RIGHT 16 15 2 1
BCK
DATA
MSB
B2
B15 LSB LSB JUSTIFIED FORMAT 16 BITS
MSB
B2
B15 LSB
WS
LEFT 18 17 16 15 2 1
RIGHT 18 17 16 15 2 1
BCK
DATA
MSB
B2
B3
B4
B17 LSB LSB JUSTIFIED FORMAT 18 BITS
MSB
B2
B3
B4
B17 LSB
WS
LEFT 20 19 18 17 16 15 2 1
RIGHT 20 19 18 17 16 15 2 1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B19 LSB LSB JUSTIFIED FORMAT 20 BITS
MSB
B2
B3
B4
B5
B6
B19 LSB
WS 24 BCK 23 22 21
LEFT 20 19 18 17 16 15 2 1 24 23 22 21
RIGHT 20 19 18 17 16 15 2 1
Preliminary specification
UDA1328T
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB LSB JUSTIFIED FORMAT 24 BITS
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MGR751
Fig.5 Serial interface; input formats.
Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
9 L3 INTERFACE DESCRIPTION Table 5 BIT 1 0 0 1 Selection of data transfer BIT 0 0 1 0
UDA1328T
The following system and digital sound processing features can be controlled in the microcontroller mode of the UDA1328: * Data input format * De-emphasis for 32, 44.1, 48 and 96 kHz * Volume control: master and for individual channels * Soft or quick mute: master and for individual channels * Output polarity control: master and for individual channels * Digital silence control: master and for individual channels * Power-down mode. The exchange of data and control information between the microcontroller and the UDA1328 is accomplished via a serial hardware interface comprising the following pins: L3DATA: microcontroller interface data line L3MODE: microcontroller interface mode line L3CLOCK: microcontroller interface clock line. Information transfer via the microcontroller bus is organized LSB first and is in accordance with the so called `L3' format, in which two different modes of operation can be distinguished. The address mode and data transfer mode are illustrated in Figs 6 and 7. The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. Data transfer for the UDA1328 can only be in one direction; input to the UDA1328 to program its sound processing and other functional features. 9.1 Address mode
TRANSFER data (volume, de-emphasis, mute, digital silence mode, polarity control) not used status (system clock frequency, data input format, mute mode, power control) not used
1
1
Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1328 is 000100 (bit 7 to bit 2) when L3ADR (DEEM0) = LOW or 000101 when L3ADR = HIGH. In the event that the UDA1328 receives a different address, it will deselect its microcontroller interface logic. 9.2 Data transfer mode
The selection preformed in the address mode remains active during subsequent data transfers, until the UDA1328 receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, shown in Fig.6. The maximum input clock and data rate is 64fs. All transfers are byte wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1328 after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.8. 9.2.1 PROGRAMMING THE SOUND PROCESSING AND
OTHER FEATURES
The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.6. Data bits 0 and 1 indicate the type of subsequent data transfer as given in Table 5.
The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode, bit 1 and bit 0 (see Table 5). The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) is the value that is placed in the selected registers. When the data transfer of type `data' is selected, the features volume, sub volume, de-emphasis, mute, digital silence settings, output polarity control and channel selection can be controlled. When the data transfer of type `status' is selected, the features system clock frequency, data input format, mute mode and power control can be controlled.
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Preliminary specification
Multi-channel filter DAC
UDA1328T
handbook, full pagewidth
L3MODE th(L3)A tsu(L3)A L3CLOCK tCLK(L3)L tCLK(L3)H tsu(L3)A
th(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.6 Timing address mode.
handbook, full pagewidth
tstp(L3)
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK
tsu(L3)DA
th(L3)DA
L3DATA WRITE
BIT 0
BIT 7
MGL882
Fig.7 Timing for data transfer mode.
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
UDA1328T
handbook, full pagewidth
tstp(L3)
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGL725
Fig.8 Multibyte transfer.
Table 6 BIT 7 0
Data transfer of type `status' BIT 6 RST BIT 5 SC1 BIT 4 SC0 BIT 3 IF2 BIT 2 IF1 BIT 1 IF0 BIT 0 0 ReSeT System Clock frequency (1 and 0) data Input Format (2 to 0) REGISTER SELECTED
1
0
0
0
0
0
QM
PC
Quick/soft Mute Power Control
Table 7 BIT 7 0 0 1
Data transfer of type `data' BIT 6 0 1 0 BIT 5 VC5 0 DE2 BIT 4 VC4 0 DE1 BIT 3 VC3 0 DE0 BIT 2 VC2 0 MT BIT 1 VC1 VQ1 DSM BIT 0 VC0 VQ0 PLC REGISTER SELECTED Volume Control (5 to 0) 0.25 dB step sub volume (1 and 0) DE-emphasis (2 to 0) MuTe Digital Silence Mode PoLarity Control
1
1
0
0
ACH
CH2
CH1
CH0
All CHannels select CHannel select (2 to 0)
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
9.2.2 RESET BIT 9.2.5 QUICK MUTE
UDA1328T
A 1-bit value to initialize the L3 registers with the default settings (except the system clock setting and the data input format setting) by writing a logic 1 to RST (see Table 6). The default settings after reset are as follows: * Mute mode: soft mute * Power: on * Volume: 0 dB * Sub volume: 0 dB * De-emphasis: off * Mute: off * Silence detect mode: detect * Polarity: non-inverting. 9.2.3 SYSTEM CLOCK FREQUENCY
A 1-bit value to set the mute mode to either soft mute (via cosine roll-off), quick or hard mute. Table 10 Quick mute QM 0 1 9.2.6 POWER CONTROL FUNCTION soft mute mode quick mute mode
A 1-bit value to disable the ADC and/or DAC to reduce power consumption. Table 11 Power control settings PC 0 1 9.3 Feature settings FUNCTION all channels off all channels on
A 2-bit value (SC1 and SC0) to select the used external clock frequency (see Table 8). Table 8 System clock frequency settings SC0 0 1 0 1 FUNCTION 512fs 384fs 256fs 768fs
SC1 0 0 1 1 9.2.4
In the UDA1328 there are features that can be controlled either per-channel or all at the same time. These features are: * Volume control * Sub volume control * Mute * Output polarity control * Digital silence detect. When a `per-channel' setting is required for these features, the ACH bit (see Table 7) must be set to logic 0 before writing a new value to one of the features. Once this has been performed a channel is selected via the CH2 to CH0 bits. The features for this channel can be controlled without sending the same channel address again (low microcontroller mode). When the ACH bit is set to logic 1, which means `all channels select', all channels will be set to the same value of the feature sent afterwards. For the digital silence detector it holds that the DS pin is either active on the selected channel when bit ACH is set to logic 0 before writing the DSM bit, or the DS pin is active on all channels when the ACH bit is set to logic 1.
DATA INPUT FORMAT
A 3-bit value (IF2 to IF0) to select the used data format (see Table 9). Table 9 IF2 0 0 0 0 1 1 1 1 Data input format settings IF1 0 0 1 1 0 0 1 1 IF0 0 1 0 1 0 1 0 1 I2S-bus LSB-justified; 16 bits LSB-justified; 18 bits LSB-justified; 20 bits MSB-justified LSB-justified; 24 bits reserved reserved FUNCTION
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
9.3.1 CHANNEL SELECTION MODE 9.3.3 SUB VOLUME CONTROL
UDA1328T
A 1-bit value to set the selection mode (either individually or per-channel) for the volume, mute, polarity control and silence detect is given in Table 12. The 3-bit value is given in Table 13. Table 12 1-bit selection ACH(1) 0 1 Note 1. For setting the de-emphasis mode, the ACH bit must be set to logic 1 before setting the de-emphasis. Table 13 3-bit selection CH2 0 0 0 0 1 1 1 1 9.3.2 CH1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 FUNCTION channel 1 selected channel 2 selected channel 3 selected channel 4 selected channel 5 selected channel 6 selected not used not used FUNCTION individual channel select; use CH(2 : 0) all channels selected
A 2-bit value to program the channel volume attenuation with a 0.25 dB step (VQ1 and VQ0). To validate the sub volume settings in these registers, the volume control registers of corresponding channels must be updated one after the other. Table 15 Sub volume settings VQ1 0 0 1 1 9.3.4 MUTE VQ0 0 1 0 1 VOLUME (dB) 0.00 -0.25 -0.50 -0.75
A 1-bit value to enable the digital mute (the type of mute is set via the QM bit in the status register). Table 16 Mute MT 0 1 9.3.5 DIGITAL SILENCE MODE FUNCTION no muting muting
VOLUME CONTROL
A 1-bit value to set the digital silence mode. This bit is set together with the channel address CH2 to CH0 and the ACH bit. When the ACH bit is set to logic 0, each channel can be selected for digital silence detection. When the ACH bit is set to logic 1 all channels are selected. Table 17 Digital silence mode
A 6-bit value to program the channel volume attenuation (VC5 to VC0). The range is 0 dB to - dB in steps of 1 dB (see Table 14). Table 14 Volume settings VC5 0 0 0 0 : 1 1 1 1 1 VC4 0 0 0 0 : 1 1 1 1 1 VC3 0 0 0 0 : 1 1 1 1 1 VC2 0 0 0 0 : 0 1 1 1 1 VC1 0 0 1 1 : 1 0 0 1 1 VC0 0 1 0 1 : 1 0 1 0 1 VOLUME (dB) 0 0 -1 -2 : -58 -59 -60 - -
DSM 0 1
FUNCTION no participation participates
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
9.3.6 DE-EMPHASIS 9.3.7 OUTPUT POLARITY CONTROL
UDA1328T
A 2-bit value to enable the digital de-emphasis filter. Table 18 De-emphasis settings DE2 0 0 0 0 1 DE1 0 0 1 1 0 DE0 0 1 0 1 0 FUNCTION no de-emphasis de-emphasis; 32 kHz de-emphasis; 44.1 kHz de-emphasis; 48 kHz de-emphasis; 96 kHz
A 1-bit value to program the output polarity of the output signal. This bit must be used together with the CH2 to CH0 bits and the ACH bit to either select the polarity for all channels or to set for each channel individually. Table 19 Output polarity control PLC 0 1 FUNCTION non-inverting inverting
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA Txtal(max) Tstg Tamb Ves PARAMETER digital supply voltage analog supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling note 2 note 3 Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor, expect pin 19 (L3DATA) which can withstand ESD pulses of -2500 to +2500 V. 3. Equivalent to discharging a 200 pF capacitor via a 0.75 H series inductor. 11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 12 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE 58 UNIT K/W CONDITIONS note 1 note 1 - - - -65 -40 -3000 -250 MIN. 5.0 5.0 150 +125 +85 +3000 +250 MAX. V V C C C V V UNIT
thermal resistance from junction to ambient in free air
13 QUALITY SPECIFICATION In accordance with "SNW-FQ-611-E". The number of the quality specification can be found in the "Quality Reference Handbook".
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
UDA1328T
14 DC CHARACTERISTICS VDDD = VDDA = 3.3 V; Tamb = 25 C; RL = 5 k. All voltages referenced to ground (pins 3 and 20); unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA IDDD VIH VIL VIL(th) VIH(th) Vhyst ILI Ci VOH VOL DAC Vref Io(max) RL CL Notes 1. All supply connections must be made to the same external power supply unit. 2. When the DAC drives a capacitive load above 50 pF, a series resistor of 100 must be used to prevent oscillations in the output operational amplifier. reference voltage maximum output current load resistance load capacitance note 2 referenced to VSSA 0.45VDDA 3 - 0.5VDDA 0.22 - - 0.55VDDA - - 50 V mA k pF (THD + N)/S < 0.1% - analog supply voltage digital supply voltage analog supply current digital supply current note 1 note 1 all channels active; operating mode operating mode 2.7 2.7 - - 2.0 - 0.9 1.4 0.4 - - IOH = -2 mA IOL = 2 mA 0.85VDDD - 3.3 3.3 28 11 - - - - - - - - - 3.6 3.6 - - - 0.8 1.45 1.9 0.7 1 10 - 0.4 V V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital input pins: 5 V tolerant TTL compatible HIGH-level input voltage LOW-level input voltage LOW-level threshold input voltage; falling edge HIGH-level threshold input voltage; rising edge Schmitt trigger hysteresis voltage input leakage current input capacitance V V V V V A pF
Digital output pin HIGH-level output voltage LOW-level output voltage V V
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
UDA1328T
15 AC CHARACTERISTICS (ANALOG) VDDD = VDDA = 3.3 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k. All voltages referenced to ground (pins 3 and 20); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - fs = 48 kHz; at 0 dB fs = 96 kHz; at 0 dB S/N signal-to-noise ratio fs = 48 kHz; code = 0; A-weighted fs = 96 kHz; code = 0; A-weighted DAC: channels 3 to 6 Vo(rms) Vo (THD + N)/S output voltage (RMS value) unbalance between channels total harmonic distortion plus noise-to-signal ratio fs = 48 kHz; at 0 dB fs = 96 kHz; at 0 dB S/N PSRR signal-to-noise ratio power supply rejection ratio fs = 48 kHz; code = 0; A-weighted fs = 96 kHz; code = 0; A-weighted fripple = 1 kHz; Vripple(p-p) = 100 mV - - - - - - - fs = 48 kHz; at -60 dB; A-weighted - fs = 96 kHz; at -60 dB; A-weighted - 1 0.1 -90 -43 -85 -41 103 101 50 - - -83 - - - - - - V dB dB dB dB dB dB dB dB - - - - fs = 48 kHz; at -60 dB; A-weighted - fs = 96 kHz; at -60 dB; A-weighted - TYP. MAX. - - -88 - - - - - UNIT
DAC: channels 1 and 2 in differential mode Vo(rms) Vo (THD + N)/S output voltage (RMS value) unbalance between channels total harmonic distortion plus noise-to-signal ratio 2 0.1 -95 -46 -90 -44 106 104 V dB dB dB dB dB dB dB
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
UDA1328T
16 AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = 2.7 to 3.6 V; Tamb = -20 to +85 C; RL = 5 k. All voltages referenced to ground (pins 3 and 20); unless otherwise specified. The typical timing is specified at 44.1 kHz sampling frequency. SYMBOL Tsys PARAMETER system clock cycle CONDITIONS fsys = 256fs fsys = 384fs fsys = 512fs fsys = 768fs; note 1 tCWL tCWH tr tf Tcy(CLK)(bit) tCLKH(bit) tCLKL(bit) tr tf tsu(i)(D) th(i)(D) tsu(WS) th(WS) Tcy(CLK)(L3) tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D tsu(L3)DA th(L3)DA tstp(L3) Note 1. In the 768fs clock mode, the sampling frequency must be limited to 55 kHz. LOW-level system clock pulse width HIGH-level system clock pulse width rise time fall time fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz MIN. 35 23 20 20 30 40 30 40 - - 140 60 60 - - 20 0 20 10 TYP. 88 59 44 30 - - - - - - - - - - - - - - - - - - - - - - - - - MAX. 780 520 390 260 70 60 70 60 20 20 - - - 20 20 - - - - - - - - - - - - - - UNIT ns ns ns ns %Tsys %Tsys %Tsys %Tsys ns ns
Serial input data timing (see Fig.9) bit clock period bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time word selection set-up time word selection hold time ns ns ns ns ns ns ns ns ns
Microcontroller interface timing (see Figs 6, 7 and 8) L3CLOCK time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time L3MODE hold time L3MODE set-up time L3MODE hold time L3DATA set-up time L3DATA hold time L3MODE halt time addressing mode addressing mode data transfer mode data transfer mode 500 250 250 190 190 190 190 ns ns ns ns ns ns ns ns ns ns
data transfer and addressing mode 190 data transfer and addressing mode 30 190
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
UDA1328T
handbook, full pagewidth
WS th(WS) tf tsu(WS)
tCLKH(bit) tr BCK tCLKL(bit) Tcy(CLK)(bit) DATAI
tsu(i)(D)
th(i)(D)
MGL721
Fig.9 Serial interface timing.
handbook, full pagewidth
t CWH
t CWL Tsys
MGR984
Fig.10 System clock timing.
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
17 APPLICATION INFORMATION
UDA1328T
handbook, full pagewidth
AGND C7 47 F (16 V) C8 47 F (16 V) 10 k 1 32 VOUT2P 10 k 5 6 VOUT4 2 31 VOUT2N 10 k 100 pF AGND C9 47 F (16 V) C10 47 F (16 V) VSSA 3 30 Vref C14 100 nF VOUT5 4 29 VOUT1N AGND 10 k VOUT6 100 nF VDDA 6 27 TEST1 AGND n.c. 7 26 DS VDDA VDDD DEEM1 100 F (16 V) 100 F (16 V) AGND 5 28 VOUT1P 10 k 100 F (16 V) 1 2 1 3 C13 47 F (16 V) 10 k 10 k 100 pF 47 F 100 VOUT1 AGND
R13 100 VOUT3 R14 10 k AGND R15 100 VOUT4 R16 10 k AGND
VOUT3
1/2 NE5532 47 F 7 (16 V)
100 VOUT2 10 k
R17 100 VOUT5 R18 10 k AGND R19 100 VOUT6 R20 10 k AGND VDDA
1/2 (16 V) NE5532 10 k
10 k
3.3 V TEST3 8 25 DEEM0 BZN32A07
UDA1328T
STATIC/L3 STATIC 9 24
AGND DGND BCK 10 23 MUTE ground WS 11 22 TEST2 AGND DGND VDDD 100 nF 1 100 F (16 V)
DATAI12
12
21
VDDD
DATAI34
13
20
VSSD
DATAI56
14
19
L3DATA
DGND
n.c. 47 SYSCLK
15
18
L3CLOCK
SYSCLK
16
17
L3MODE
MGR983
Fig.11 Application diagram.
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
18 PACKAGE OUTLINE SO32: plastic small outline package; 32 leads; body width 7.5 mm
UDA1328T
SOT287-1
D
E
A X
c y HE vM A
Z 32 17
Q A2 A1 pin 1 index Lp 1 e bp 16 wM L detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 0.02 0.01 c 0.27 0.18 0.011 0.007 D (1) 20.7 20.3 0.81 0.80 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.419 0.394 L 1.4 0.055 Lp 1.1 0.4 0.043 0.016 Q 1.2 1.0 0.047 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.95 0.55 0.037 0.022
0.012 0.096 0.004 0.086
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC MO-119 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
19 SOLDERING 19.1 Introduction to soldering surface mount packages
UDA1328T
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 19.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 19.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
19.5 Suitability of surface mount IC packages for wave and reflow soldering methods
UDA1328T
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 20 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 21 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
NOTES
UDA1328T
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
NOTES
UDA1328T
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Philips Semiconductors
Preliminary specification
Multi-channel filter DAC
NOTES
UDA1328T
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/25/02/pp28
Date of release: 2000
Jan 04
Document order number:
9397 750 06677

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